\doxysection{ARM\+\_\+\+MPU\+\_\+\+Region\+\_\+t Struct Reference}
\hypertarget{struct_a_r_m___m_p_u___region__t}{}\label{struct_a_r_m___m_p_u___region__t}\index{ARM\_MPU\_Region\_t@{ARM\_MPU\_Region\_t}}


{\ttfamily \#include $<$mpu\+\_\+armv7.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_r_m___m_p_u___region__t_afe7a7721aa08988d915670efa432cdd2}{RBAR}}
\begin{DoxyCompactList}\small\item\em The region base address register value (RBAR) \end{DoxyCompactList}\item 
\Hypertarget{struct_a_r_m___m_p_u___region__t_a38c1d3bc6a9ffc9423d633add01928f1}\label{struct_a_r_m___m_p_u___region__t_a38c1d3bc6a9ffc9423d633add01928f1} 
uint32\+\_\+t {\bfseries RASR}
\begin{DoxyCompactList}\small\item\em The region attribute and size register value (RASR) MPU\+\_\+\+RASR. \end{DoxyCompactList}\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_r_m___m_p_u___region__t_ab5d3a650dbffd0b272bf7df5b140e8a8}{RLAR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Struct for a single MPU Region 

\label{doc-variable-members}
\Hypertarget{struct_a_r_m___m_p_u___region__t_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_a_r_m___m_p_u___region__t_afe7a7721aa08988d915670efa432cdd2}\index{ARM\_MPU\_Region\_t@{ARM\_MPU\_Region\_t}!RBAR@{RBAR}}
\index{RBAR@{RBAR}!ARM\_MPU\_Region\_t@{ARM\_MPU\_Region\_t}}
\doxysubsubsection{\texorpdfstring{RBAR}{RBAR}}
{\footnotesize\ttfamily \label{struct_a_r_m___m_p_u___region__t_afe7a7721aa08988d915670efa432cdd2} 
uint32\+\_\+t ARM\+\_\+\+MPU\+\_\+\+Region\+\_\+t\+::\+RBAR}



The region base address register value (RBAR) 

Region Base Address Register value \Hypertarget{struct_a_r_m___m_p_u___region__t_ab5d3a650dbffd0b272bf7df5b140e8a8}\index{ARM\_MPU\_Region\_t@{ARM\_MPU\_Region\_t}!RLAR@{RLAR}}
\index{RLAR@{RLAR}!ARM\_MPU\_Region\_t@{ARM\_MPU\_Region\_t}}
\doxysubsubsection{\texorpdfstring{RLAR}{RLAR}}
{\footnotesize\ttfamily \label{struct_a_r_m___m_p_u___region__t_ab5d3a650dbffd0b272bf7df5b140e8a8} 
uint32\+\_\+t ARM\+\_\+\+MPU\+\_\+\+Region\+\_\+t\+::\+RLAR}

Region Limit Address Register value 

The documentation for this struct was generated from the following files\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/mpu\+\_\+armv7.\+h\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Include/mpu\+\_\+armv8.\+h\end{DoxyCompactItemize}
